1. Field of the Invention
The present invention relates to microelectronic devices and, in particular, to a silicon germanium-based circuit and network configuration to reduce harmful effects of electrostatic discharge in such devices.
2. Description of Related Art
Electrostatic discharge (ESD) phenomenon causes high voltage and/or current to be impressed across the terminals of microelectronic and other devices. Both voltage and the current spikes, usually of very short duration, can break down the isolation or diffusions in various portions of individual such devices, thus rendering the device completely or partially inoperable.
The energy spectrum as a function of frequency of an ESD event is a function of the ESD phenomenon. There are three models in use to describe ESD: the human body model (HBM), the machine model (MM), and the charge device model (CDM). In the human body model, a 4 KV pulse is assumed with a maximum current of 2.6 amperes with a 150 ns event time. In the 400 volt machine model, a maximum of 7 amperes is assumed with a 10-50 ns event time. In the charge device model, voltages as high as 1 KV and currents of 9 to 10 amperes with 0.25 ns event times are assumed. For the CDM mechanism, the energy spectrum is contained within the 0 to 5 GHz frequencies regime with negligible energy beyond 5 GHz. In general, ESD events occur at frequencies lower than 5 GHz. There is a need for ESD protection systems which function without impacting the functional performance of the active and passive elements"" chip performance. In an integrated semiconductor chip, core and peripheral circuitry have high frequency device components. For example, the high speed transistor of a SiGe technology can be between 50 GHz to 100 GHz. For a SiGeC technology transistor, levels of 100 to 150 GHz are obtainable. Hence there is a desire to have an ESD element which is faster than the ESD HBM, MM, and CDM phenomenon (f greater than 5 GHz) and whose cutoff frequency is less than the high speed functional transistor.
Capacitive loading becomes a major concern for microelectronic chips running at RF frequencies, i.e., frequencies greater than 1 GHz, as the capacitive loading of conventional ESD devices has an adverse effect on device performance. The total capacitance looking into a device is the sum of the ESD device and the circuit capacitances:
CTOT=CCKT+CESD
RF circuits are designed with low capacitance, but ESD circuits and devices have relatively high capacitances. CTOT can become driven by CESD and the chip fails to perform. For example, at 1 GHz a capacitance of 1 pF is acceptable, but at 10 GHz the capacitance must be in the order of 0.1 pF, which is difficult to achieve, and for 100 GHz the capacitance would need to be around 0.01 pF, which is very difficult if impossible to achieve with conventional ESD protection circuits.
Integrated circuit performance improvements continue to drive technological advances such as the implementation of silicon germanium (SiGe) based semiconductor circuitry due to its high frequency attributes and small chip size designs. With such reductions in chip size the ESD protection pad structure must be enlarged to compensate for the limited ability to get enough current discharge from small chips due to the limited umber of I/Os. However, such enlarged ESD pad structures cause detrimental capacitive loading effects which distort frequency and impact chip performance. Data comparing performance of SiGe devices over wide frequency ranges indicates significant performance degradation for those with ESD protection versus those without. There is need for an ESD protection system which functions without impacting non-ESD device performance, to discharge power to ground intended for high frequency applications.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a system for an improved ESD protection system for microelectronic devices.
It is another object of the present invention to provide ESD protection for SiGe devices which does not degrade the performance of such devices.
A further object of the invention is to provide a circuit and network which prevents harmful voltage and current spikes for microelectronic devices.
It is yet another object of the present invention to provide ESD protection for digital, analog and radio frequency (RF) applications.
It is another object of the present invention to provide ESD protection for mixed voltage and mixed signal applications.
Another object of the present invention is to provide an ESD element which is faster than the ESD HBM, MM, and CDM phenomenon (f greater than 5 GHz) and whose cutoff frequency is less than the high speed functional transistor.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a silicon-germanium ESD element comprising a substrate of a first dopant type coupled to a first voltage terminal and a first diode-configured element. The first diode-configured element has a collector region of a second dopant type in the substrate, a SiGe base layer of the first dopant type on the collector region, with the SiGe base layer including a base contact region, and an emitter of the second dopant type on the SiGe base layer. Preferably, the SiGe base layer ion collector region is an epitaxial SiGe layer and the second dopant type of the emitter is diffused in to the SiGe base layer.
The ESD element of the present invention may further include a second diode-configured element of the same structure as the first diode-configured element, with an isolation region in the substrate separating the first and second diode-configured elements. The first and second diode-configured elements form a diode network. The isolation region may be a shallow trench isolation or a deep trench isolation.
In a first preferred embodiment, the present invention provides a diode network comprising a substrate of a first dopant type coupled to a first voltage terminal and a first diode element and a second diode element. Each diode element has a collector region of a second dopant type in the substrate, a SiGe base layer of the first dopant type on the collector region, with the SiGe base layer including a base contact region, an emitter of the second dopant type on the SiGe base layer, and a circuit electrically coupling the emitter to the base contact region. An input pad is coupled to the coupled emitters/contact regions of the first and second diode elements, and the collector region of the first diode element is coupled to a second voltage terminal. The SiGe base layer of the first diode element comprises an anode of the first diode element and the collector region of the first diode element comprises a cathode of the first diode element. The collector region of the second diode element is coupled to the input pad, so that the substrate comprises an anode of the second diode element and the collector region of the second diode element comprises a cathode of the second diode element.
In a second preferred embodiment, the invention provides a diode network comprising a substrate of a first dopant type coupled to a first voltage terminal and a first diode element and a second diode element. Each diode element has a collector region of a second dopant type in the substrate, a SiGe base layer of the first dopant type on the collector region, with the SiGe base layer including a base contact region, and an emitter of the second dopant type on the SiGe base layer. A circuit electrically couples the emitter to the base contact region in the first diode element and a circuit electrically couples the emitter in the second diode element to the substrate and first voltage terminal. An input pad is coupled to the coupled emitters/contact region of the first diode element and the collector region of the second diode element. The collector region of the first diode element is coupled to a second voltage terminal, so that the SiGe base layer of the first diode element comprises an anode of the first diode element and the collector region of the first diode element comprises a cathode of the first diode element. The collector region of the second diode element is coupled to the input pad, so that the SiGe base layer comprises an anode of the second diode element and the collector region of the second diode element comprises a cathode of the second diode element.
In another embodiment of the present invention, there is provided a diode network comprising a substrate of a first dopant type coupled to a first voltage terminal and a first diode element and a second diode element. Each diode element has a collector region of a second dopant type in the substrate, a SiGe base layer of the first dopant type on the collector region, with the SiGe base layer including a base contact region, and an emitter of the second dopant type on the SiGe base layer. A circuit electrically couples the emitter to the base contact region and an input pad is coupled to the coupled emitters/contact region of the second diode element. The collector region of the first diode element is coupled to a second voltage terminal, so that the SiGe base layer of the first diode element comprises an anode of the first diode element and the collector region of the first diode element comprises a cathode of the first diode element. The collector region of the second diode element is coupled to the coupled emitters/contact region of the first diode element, so that the SiGe base layer of the second diode element comprises an anode of the second diode element and the collector region of the second diode element comprises a cathode of the second diode element.
A further embodiment of the present invention provides a diode comprising a substrate of a first dopant type coupled to a first voltage terminal and a diode element. The diode element has a collector region of a second dopant type in the substrate, a SiGe base layer of the first dopant type on the collector region, with the SiGe base layer including a base contact region, and an emitter of the second dopant type on the SiGe base layer. The collector region of the diode element is coupled to an input pad and the emitter of the diode element is coupled to a second voltage terminal, so that the substrate comprises an anode of the diode element and the collector region comprises a cathode of the diode element.
Yet another embodiment of the present invention provides a diode comprising a substrate of a first dopant type coupled to a first voltage terminal and a diode element having a collector region of a second dopant type in the substrate, a SiGe base layer of the first dopant type on the collector region, with the SiGe base layer including a base contact region, and an emitter of the second dopant type on the SiGe base layer. An input pad is coupled to the SiGe base layer, the collector region of the diode element is coupled to both the input pad and the base layer, and the emitter of the diode element coupled to a second voltage terminal, so that the substrate comprises an anode of the diode element and the collector region comprises a cathode of the diode element.
The present invention provides a further embodiment of a diode network comprising a substrate of a first dopant type coupled to a first voltage terminal and a plurality of diode elements. Each diode element has a collector region of a second dopant type in the substrate, with each collector region being coupled to the first voltage terminal, a SiGe base layer of the first dopant type on the collector region, with the SiGe base layer including a base contact region and an emitter of the second dopant type on the SiGe base layer. An input pad is coupled to the emitter of a first one of the diode elements and there is provided a plurality of clamping elements coupled in series. The base layer of each diode element is coupled to the emitter of an adjacent diode element, except for the base layer of a last one of the diode elements which is coupled to a second rail voltage source, and each of the clamping elements is connected across the coupled base-emitters of adjacent diode elements. The clamping elements may be one or more of elements such as reach through resistors, silicon germanium polysilicon resistors, silicon germanium npns, or silicon germanium pnps.
Another embodiment of the present invention provides a diode network comprising a substrate of a first dopant type coupled to a first voltage terminal and a plurality of diode elements. Each diode element has a collector region of a second dopant type in the substrate, with each collector region being coupled to the first voltage terminal, a SiGe base layer of the first dopant type on the collector region, with the SiGe base layer including a base contact region and an emitter of the second dopant type on the SiGe base layer. An input pad is coupled to the emitter of a first one of the plurality of diode elements and the base layer of each of the plurality of diode elements is coupled to the emitter of an adjacent one of the plurality of diode elements, except for the base layer of a last one of the plurality of diode elements which is coupled to the second voltage terminal. The diode network also includes a further diode element having the base layer coupled to the base layer of the last of the plurality of diode elements, a collector region coupled to the first voltage terminal, and the emitter coupled to the second voltage terminal.
In a further embodiment, the present invention provides a diode network comprising a substrate of a first dopant type coupled to a first voltage terminal and a plurality of diode elements. Each diode element has a collector region of a second dopant type in the substrate, a SiGe base layer of the first dopant type on the collector region, with the SiGe base layer including a base contact region and an emitter of the second dopant type on the SiGe base layer. An input pad is coupled to the base layer of a first one of the diode elements and the emitter of each of the diode elements is coupled to the base layer of an adjacent diode element, except for the emitter of a last one of the diode elements which is coupled to a second rail voltage source. Each collector region is coupled to a common collector voltage terminal, or to different terminals.
In each of the embodiments, the isolation regions may be disposed adjacent the collector regions of the diode elements and below a portion of the SiGe base layer of the diode elements. The SiGe base layer in the diode elements preferably comprises an active, single crystal layer in a portion directly over the collector region and a polycrystalline layer in portions directly over the isolation regions.
Yet another embodiment of the present invention provides a frequency cutoff ESD protection network for high frequency applications. The network comprises a first device on a chip having circuitry with a first frequency response and a second device on the chip having circuitry with a second frequency response, the second frequency response being less than the first frequency response. Preferably, at least one of the devices is a SiGe device, and both the first and second devices may be SiGe devices. More preferably, one or both of the first and second devices comprises a substrate of a first dopant type coupled to a first voltage terminal and a diode-configured element. The diode-configured element has a collector region of a second dopant type in the substrate; a SiGe base layer of the first dopant type on the collector region, the SiGe base layer including a base contact region; and an emitter of the second dopant type on the SiGe base layer. The second device preferably has circuitry having a second frequency greater than 5 GHz.